1. Field of the Invention
The present invention relates to pixel cell structures and pixel cell arrays, and more particularly, to pixel cells and pixel cell arrays having improved leakage and performance characteristics.
2. Description of the Related Art
Pixel cells convert incident light energy into corresponding electrical signals that can be processed and measured. In particular, U.S. Pat. No. 5,324,958 to Mead, et al. discloses a pixel cell structure formed from a bipolar phototransistor. A cross-section of this conventional pixel cell structure is shown in FIG. 1.
Conventional NPN bipolar phototransistor 10 is formed within N type well 12 present within lightly doped P type substrate 14. N well 12 serves as the collector of bipolar transistor 10. Lightly doped P type region 16 is created inside N well 12 and serves as the base of bipolar phototransistor 10. Heavily doped N type region 18 is created within lightly P doped type base 16 and serves as the emitter of bipolar transistor 10. Electrically active base 16, emitter 18, and collector 12 regions of conventional pixel cell 10 are isolated from adjacent pixel cells by field oxide structures 20. Thin oxide layer 22 is formed over field oxide 20 and lightly doped P type base 16. Thin oxide layer 22 acts as the dielectric layer of a capacitor having polysilicon 24 and base 16 as plates. In this manner, polysilicon layer 24 is capacitively coupled with base 16 through thin oxide layer 22, and drives base 16. Polysilicon layer 24 also serves as a portion of a row-select line. Emitter contact 26 (typically aluminum metal) is formed on top of heavily doped N type emitter region 18 and is in electrical communication with a column-sense line (not shown). N well 12 is in electrical communication with a positive supply voltage (not shown).
Under normal operation, a charge generated by light incident on the surface of the pixel cell collects during an integration time period, and is subsequently read out to indicate the intensity of the incident light. Specifically, photons 28 incident on the surface of pixel cell 10 pass though polysilicon layer 24 and enter lightly doped P type base 16 during an integration time period. These incident photons generate electron/hole pairs within lightly doped P type base 16.
Polysilicon 24 is maintained at a relatively low voltage during the integration time period. Because base 16 is capacitively coupled with polysilicon 24, base 16 is maintained at a relatively low base voltage during the integration time period, so that holes generated by the passage of incident photons collect in base 16. Electrons generated by the impact of incident photons drift away to N type emitter region 18 or collector region 12.
At the conclusion of the integration period, the voltage applied to polysilicon 24 is increased. The corresponding positive voltage change that is communicated to base 16 through thin oxide 22 permits current to flow from base 16 into emitter 18. Thus, holes that have collected in base 16 during the integration period, multiplied by the current gain of bipolar transistor 10, flow from base 16 into emitter 18. This flow of holes is output through emitter contact 26 onto the column-sense line, and can be detected to determine the quantity of incident photons.
FIG. 2 shows an array 224 of conventional pixel cells 210 forming part of imaging device 212. Rows of individual pixel cells 210 share common row select lines 214, and columns of individual pixel cells 210 share common column-sense lines 216. The thin oxide layer 215 between the base 217 and the polysilicon 219 functions as the dielectric layer of a capacitor 218. The collector region underlying the pixel cells is connected to a positive supply voltage 220. Field oxide structures 222 are present in the inter-pixel regions. The electrical isolation provided by field oxide structures 222 ensures that operation of each pixel cell 210 is unaffected by electrical fields generated by nearby pixel cells.
While functional, pixel cell 10 shown in FIG. 1 and pixel cell array 224 shown in FIG. 2 suffer from a number of disadvantages.
A first disadvantage associated with conventional pixel cell 10 is unwanted formation of an inversion layer in base 16 at a depth below the interface with thin oxide 22.
Base 16 is conventionally formed by implanting dopant into the silicon prior to the formation of polysilicon 24. Subsequently, thin oxide 22 and polysilicon 24 are created on top of base 16, and emitter region 18 is formed within base 16 by high dosage, low-energy implant of conductivity-altering dopant of a type opposite that of the base.
FIG. 3A plots dopant concentration versus depth below the silicon surface in the emitter region, resulting from high energy implantation of P type dopant prior to the formation of polysilicon. FIG. 3A reveals that high energy implantation of P type dopant to form the base, results in highest P type dopant concentration lying at a depth Z below the silicon surface. The dopant profile shown in FIG. 3A is advantageous for pixel cell device 10 because 1) regions shallower than Z contain less P type dopant, and are thus available to receive concentrated N type dopant to form the emitter; 2) the P type dopant extends deeply into the silicon, and thereby isolates the emitter region; and 3) the interface between highest N and P type dopant levels is abrupt and clearly defined, allowing for optimum P/N junction performance.
Unfortunately, formation of base 16 by high energy implant prior to the formation of polysilicon may cause an inversion layer to form underneath the thin oxide layer 22. FIG. 3B plots dopant concentration versus depth below the silicon surface in the base region underlying the thin oxide, resulting from high energy implantation of P type dopant prior to the formation of polysilicon. As with FIG. 3A, FIG. 3B reveals that high energy implantation creates highest P type dopant concentrations at a depth Z below the surface of the silicon. However, optimum capacitive coupling between base 16 and polysilicon 24 of NPN bipolar phototransistor 10 occurs where silicon in base 16 immediately beneath thin oxide 22 operates in a state of accumulation, wherein majority carriers are plentiful and are able to gather at a minimum distance from polysilicon 24. In NPN bipolar phototransistor 10, holes are the majority carriers in base 16, and must encounter P type dopant at the thin oxide interface in order to ensure optimal capacitive coupling between base 16 and polysilicon 24.
Unfortunately however, FIG. 3B reveals that high energy implant of P type dopant creates the most concentrated level of P type dopant at a depth Z below the surface of the silicon. Having the dopant concentrated at a depth Z below the surface leaves insufficient doping near the surface, such that the majority carriers easily become depleted near the surface. This state of depletion, as opposed to the state of accumulation in which carriers are plentiful, reduces the capacitive coupling between base 16 and polysilicon 24. If the dopant concentration of the base implant is very low relative to the collector dopant concentration near the surface, it is even possible, for sufficiently high voltage on polysilicon 24, for the surface area to be in a state of inversion, in which minority carriers are drawn into the surface region and cause unwanted conduction between the nearby regions of the other conductivity type, i.e., between collector and emitter.
FIG. 3C plots dopant concentration versus depth below the silicon surface in the emitter region, resulting from the alternative prior art method of low energy implantation of P type dopant to form the base prior to the formation of polysilicon. FIG. 3D plots dopant concentration versus depth below the silicon surface in the base region underlying the thin oxide, resulting from low energy implantation of P type dopant to form the base prior to the formation of polysilicon.
FIG. 3D indicates that utilization of a low energy implant no longer creates a depletion or inversion region, as P type dopant concentrations in base 16 are sufficiently high at the thin oxide interface.
Unfortunately however, FIG. 3C reveals that low energy implantation of P type dopant to form base 16 places the highest concentration of P type dopant at a relatively shallow depth that may later lie within the emitter. The dopant profile shown in FIG. 3C forces the subsequent N type emitter implant to overcome these high levels of P type dopant, and also blurs the P/N junction, resulting in less efficient operation of the base and emitter of bipolar phototransistor 10. Low energy implant of P type dopant as shown in FIGS. 3C and 3D also makes the overall base region more shallow, resulting in less effective isolation of the emitter region from the underlying collector.
Therefore, it is desirable to fabricate a bipolar phototransistor having a base dopant profile that incorporates the best features of the high energy implant shown in FIG. 3A near the emitter, and the best features of the low energy implant shown in FIG. 3D in the region outside the emitter under the thin oxide.
A second disadvantage associated with conventional pixel cell 10 is leakage of current at the edge of emitter region 18. FIG. 4 shows an enlarged view of the junction between emitter region 18 and base 16 of conventional NPN bipolar phototransistor pixel cell 10. During operation of pixel cell 10, relatively high voltages are present at both heavily doped N type emitter region 18 and polysilicon 24. Edge 18a of the emitter region 18 adjacent to polysilicon 24 is therefore subjected to particularly high electric fields. As a result of these intense electric fields, leakage can occur between edge 18a of N+ emitter region 18, and polysilicon 24.
Therefore, it is desirable to design a pixel cell wherein the size of the heavily doped portion of the emitter region is reduced, increasing the distance between the edge of the emitter and adjacent polysilicon and thereby suppressing leakage between these points.
A third disadvantage associated with conventional NPN bipolar phototransistor pixel cell 10 is leakage of current at the field oxide interface. FIG. 5 shows an enlarged view of the interface between base 16 and field oxide 20 of conventional pixel cell 10.
While field oxide 20 is relatively thick in most places, edge 20a of the field oxide 20 thins to a narrow and relatively fragile "bird's beak" structure 20b. Formation of "bird's beak" 20b is an inevitable result of conventional field oxide growth processes. However, because of the relatively small oxide thickness present at edge 20a of field oxide 20, region 20a is exposed to particularly high electric fields during the conventional operation of pixel cell 10. The relative fragility of bird's beak 20b renders this region especially vulnerable to leakage.
Therefore, it is desirable to create a pixel cell structure that eliminates the field oxide edge as a potential source of leakage.
A fourth disadvantage associated with conventional pixel cell 10 is high resistance occurring at the point of contact between the pixel cell and the row-select and column-sense lines that link the pixel cell to the pixel cell array. Resistance of the polysilicon 24 may elevate the amount of voltage required on the row-select line in order to manipulate the pixel cell via capacitive coupling with the base, thereby needlessly subjecting the device to additional strain. Resistance between emitter contact 26 and the emitter region 18 may distort the integrity of the integration charge output to the column-sense line.
Therefore, it is desirable to design a pixel cell having low resistance contacts with the rows-select and column-sense lines.